The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling alone is not sufficient to provide the logic capacity and on-chip resources required to meet industry demands.
To address this limitation, 3D integrated circuits (3D ICs) have been introduced. 3D ICs offer improved performance (e.g., increased logic capacity, more internal memory, reduced latency, etc.) as well as heterogeneous functionality (e.g., logic, memory, etc.) in a reduced form factor. In some 3D IC examples, passive silicon interposers (e.g., with microbumps and through-silicon vias) are used to combine multiple die in a single package. As such, die of different types and/or die manufactured using different silicon processes may be interconnected on the interposer. In particular, to meet the high density routing needs of the multiple interconnected die, the interposer may be designed using metal interconnect layers having a high-density and fine metal pitch to complete all the required signal routing. Further, to meet the increasing memory bandwidth demand, high-bandwidth memory (HBM) has been introduced for use in 3D ICs. However, the integration of HBM with 3D ICs has been a challenge at least because of the high HBM RC delays associated with the high-density, fine metal pitch interconnect layers of the interposer. Increasing the size of the interposer interconnect layers (e.g., line width) may reduce resistance, but doing so would also increase inter-metal capacitance and would require a larger metal pitch, which cannot be used to meet both high-speed (e.g., for HBM) and high-density (e.g., as in FPGAs and SOCs) interconnect requirements.
Accordingly, there is a need for improved systems providing interposer structures.